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features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 130 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 20 mips throughput at 20 mhz ? on-chip 2-cycle multiplier ? non-volatile program and data memories ? in-system self-programmable flash, endurance: 10,000 write/erase cycles 32k bytes ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-w rite operation ? eeprom, endurance: 100, 000 write/er ase cycles 1k bytes ? internal sram 2k bytes ? programming lock for software security ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities a ccording to the jtag standard ? extensive on-chip debug support ? programming of flas h, eeprom, fuses, and lock bits through the jtag interface ? peripheral features ? two 8-bit timer/counte rs with separate prescaler and compare mode ? one 16-bit timer/counter with separate prescaler, compare mode, and capture mode ? real time counter with separate oscillator ?four pwm channels ? 8-channel, 10-bit adc ? programmable serial usart ? master/slave spi serial interface ? universal serial interface with start condition detector ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated oscillator ? external and internal interrupt sources ? five sleep modes: idle, adc noise re duction, power-save, power-down, and standby ? i/o and packages ? 54/69 programmable i/o lines ? 64-lead tqfp, 64-pad qf n/mlf, and 100-lead tqfp ? speed grade: ? atmega325pv/atmega3250pv: 0 - 4 mhz @ 1.8 - 5.5v, 0 - 10 mhz @ 2.7 - 5.5v ? atmega325p/3250p: 0 - 10 mhz @ 2.7 - 5.5v, 0 - 10 mhz @ 4.5 - 5.5v ? temperature range: ? -40c to 85c industrial ? ultra-low power consumption ? active mode: 420a at 1 mhz, 1.8v ? power-down mode: 40 na at 1.8v ? power-save mode: 750 na at 1.8v 8-bit microcontroller with 32k bytes in-system programmable flash atmega325p/v atmega3250p/v preliminary summary 8023as?avr?12/06
2 8023as?avr?12/06 atmega325p/3250p 1. pin configurations figure 1-1. pinout atmega3250p (oc2a/pcint15) pb7 dnc (t1) pg3 (t0) pg4 reset/pg5 v cc gnd (tosc2) xtal2 (tosc1) xtal1 dnc dnc (pcint26) pj2 (pcint27) pj3 (pcint2 8 ) pj4 (pcint29) pj5 (pcint30) pj6 dnc (icp1) pd0 (int0) pd1 pd2 pd3 pd4 pd5 pd6 pd7 a v cc agnd aref pf0 (adc0) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms) pf6 (adc6/tdo) pf7 (adc7/tdi) dnc dnc ph7 (pcint23) ph6 (pcint22) ph5 (pcint21) ph4 (pcint20) dnc dnc gnd v cc dnc pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pg2 pc7 pc6 dnc ph3 (pcint19) ph2 (pcint1 8 ) ph1 (pcint17) ph0 (pcint16) dnc dnc dnc dnc pc5 pc4 pc3 pc2 pc1 pc0 pg1 pg0 index corner atme g a 3 250 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 8 19 20 21 22 23 24 25 26 27 2 8 29 30 31 32 33 34 35 36 37 3 8 39 40 41 42 43 44 45 46 47 4 8 49 50 75 74 73 72 71 70 69 6 8 67 66 65 64 63 62 61 60 59 5 8 57 56 55 54 53 52 51 100 99 9 8 97 96 95 94 93 92 91 90 8 9 88 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 79 7 8 77 76 dnc (rxd/pcint0) pe0 (txd/pcint1) pe1 (xck/ain0/pcint2) pe2 (ain1/pcint3) pe3 (usck/scl/pcint4) pe4 (di/sda/pcint5) pe5 (do/pcint6) pe6 (clko/pcint7) pe7 v cc gnd dnc (pcint24) pj0 (pcint25) pj1 dnc dnc dnc dnc (ss/pcint 8 ) pb0 (sck/pcint9) pb1 (mosi/pcint10) pb2 (miso/pcint11) pb3 (oc0a/pcint12) pb4 (oc1a/pcint13) pb5 (oc1b/pcint14) pb6 tqfp
3 8023as?avr?12/06 atmega325p/3250p figure 1-2. pinout atmega325p n ote: the large center pad underneath the qf n /mlf packages is made of metal and internally con- nected to g n d. it should be soldered or glued to the board to ensure good mechanical stability. if the center pad is left unc onnected, the package might loosen from the board. 1.1 disclaimer typical values contained in this datasheet ar e based on simulations and characterization of other avr microcontrollers manufactured on the same process technology. min and max values will be available after the device is characterized. 2. overview the atmega325p/3250p is a low-power cmos 8-bit microcon troller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the atmega325p/3250p achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. pc0 v cc gnd pf0 (adc0) pf7 (adc7/tdi) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms) pf6 (adc6/tdo) aref gnd a v cc 17 61 60 1 8 59 20 5 8 19 21 57 22 56 23 55 24 54 25 53 26 52 27 51 29 2 8 50 49 32 31 30 (rxd/pcint0) pe0 (txd/pcint1) pe1 dnc (xck/ain0/pcint2) pe2 (ain1/pcint3) pe3 (usck/scl/pcint4) pe4 (di/sda/pcint5) pe5 (do/pcint6) pe6 (clko/pcint7) pe7 (sck/pcint9) pb1 (mosi/pcint10) pb2 (miso/pcint11) pb3 (oc0a/pcint12) pb4 (oc2a/pcint15) pb7 (t1) pg3 (oc1b/pcint14) pb6 (t0) pg4 (oc1a/pcint13) pb5 pc1 pg0 pd7 pc2 pc3 pc4 pc5 pc6 pc7 pa 7 pg2 pa 6 pa 5 pa 4 pa 3 pa 0 pa 1 pa 2 pg1 pd6 pd5 pd4 pd3 pd2 (int0) pd1 (icp1) pd0 (tosc1) xtal1 (tosc2) xtal2 reset/pg5 gnd v cc index corner (ss/pcint 8 ) pb0 2 3 1 4 5 6 7 8 9 10 11 12 13 14 16 15 64 63 62 47 46 4 8 45 44 43 42 41 40 39 3 8 37 36 35 33 34 atme g a 3 25
4 8023as?avr?12/06 atmega325p/3250p 2.1 block diagram figure 2-1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. program cou n ter i n ter n al oscillator watchdog timer stack poi n ter program flash mcu co n trol register sram ge n eral purpose registers i n structio n register timer/ cou n ters i n structio n decoder data dir. reg. portb data dir. reg. porte data dir. reg. porta data dir. reg. portd data register portb data register porte data register porta data register portd timi n g a n d co n trol oscillator i n terrupt u n it eeprom spi usart status register z y x alu portb drivers porte drivers porta drivers portf drivers portd drivers portc drivers pb0 - pb7 pe0 - pe7 pa0 - pa7 pf0 - pf7 vcc g n d xtal1 xtal2 co n trol li n es + - a n alog comp arator pc0 - pc7 8-bit data bus reset calib. osc data dir. reg. portc data register portc o n -chip debug jtag tap programmi n g logic bou n dary- sca n data dir. reg. portf data register portf adc pd0 - pd7 data dir. reg. portg data reg. portg portg drivers pg0 - pg4 ag n d aref avcc u n iversal serial i n terface avr cpu porth drivers ph0 - ph7 data dir. reg. porth data register porth portj drivers pj0 - pj6 data dir. reg. portj data register portj
5 8023as?avr?12/06 atmega325p/3250p the atmega325p/3250p provides the following f eatures: 32k bytes of in-system programma- ble flash with read-while-write capabilities, 1k bytes eeprom, 2k byte sram, 54/69 general purpose i/o lines, 32 general purpose working r egisters, a jtag interface for boundary-scan, on-chip debugging support and programming, three flexible timer/counters with compare modes, internal and external interrupts, a serial programmable usart, universal serial inter- face with start condition detector, an 8-channel, 10-bit adc, a programmable watchdog timer with internal oscillator, an spi serial port, and five software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi port, and interrupt sys- tem to continue functioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions unt il the next interrupt or hardware reset. in power- save mode, the asynchronous timer, allowing the user to maintain a timer base while the rest of the device is sleeping. the adc n oise reduction mode stops the cpu and all i/o modules except asynchronous timer and adc, to minimi ze switching noise during adc conversions. in standby mode, the crystal/ resonator oscillator is ru nning while the rest of the device is sleeping. this allows very fast start-up combined with low-power consumption. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip in-system re-programmable (isp) flash allows the program memory to be repro- grammed in-system through an spi serial interf ace, by a conventional non-volatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application progr am in the application flash memory. soft- ware in the boot flash section will continue to run while the application flas h section is updated, providing true read-while-write operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic ch ip, the atmel atmega325p/3250p is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded con- trol applications. the atmega325p/3250p avr is supported with a full suite of program and system develop- ment tools including: c compile rs, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 2.2 comparison between atmega325p and atmega3250p the atmega325p and atmega3250p differs only in memory sizes, pin count and pinout. table 2-1 on page 5 summarizes the different configurations for the four devices. table 2-1. configuration summary device flash eeprom ram general purpose i/o pins atmega325p 32k bytes 1k bytes 2k bytes 54 atmega3250p 32k bytes 1k bytes 2k bytes 69
6 8023as?avr?12/06 atmega325p/3250p 2.3 pin descriptions the following section describes the i/o-pin special functions. 2.3.1 v cc digital supply voltage. 2.3.2 gnd ground. 2.3.3 port a (pa7..pa0) port a is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. 2.3.4 port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b has better driving capabilities than the other ports. port b also serves the functions of various special features of the atmega325p/3250p as listed on page 72 . 2.3.5 port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port c pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. 2.3.6 port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port d pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the atmega325p/3250p as listed on page 75 . 2.3.7 port e (pe7..pe0) port e is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port e output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port e pi ns that are externally pulled low will source current if the pull-up
7 8023as?avr?12/06 atmega325p/3250p resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e also serves the functions of various special features of the atmega325p/3250p as listed on page 76 . 2.3.8 port f (pf7..pf0) port f serves as the analog inputs to the a/d converter. port f also serves as an 8-bit bi-directional i/o port, if the a/d converter is not used. port pins can provide internal pull-up resistors (selected for each bit). the port f output buffers have sym- metrical drive characteristics with both high sink and source capa bility. as inputs, port f pins that are externally pulled low will source current if the pull-up resistors are ac tivated. the port f pins are tri-stated when a reset condition becomes active, even if the clock is not running. if the jtag interface is enabled, the pull-up resistors on pins pf7( tdi), pf5(tms), and pf4(tck) will be activated even if a reset occurs. port f also serves the functions of the jtag interface. 2.3.9 port g (pg5..pg0) port g is a 6-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port g output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port g pins that are extern ally pulled low will sour ce current if the pull-up resistors are activated. the port g pins are tri-stated when a reset condition becomes active, even if the clock is not running. port g also serves the functions of various spec ial features of the atmega325p/3250p as listed on page 76 . 2.3.10 port h (ph7..ph0) port h is a 8-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port h output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port h pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port h pins are tri-stated when a reset condition becomes active, even if the clock is not running. port h also serves the functions of various special features of the atmega3250p as listed on page 76 . 2.3.11 port j (pj6..pj0) port j is a 7-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port j output buffers have symmetrical drive characteristics with both high sink and source capa- bility. as inputs, port j pins that are externally pulled low will source current if the pull-up resistors are activated. the port j pins are tr i-stated when a reset condition becomes active, even if the clock is not running. port j also serves the functions of various special features of the atmega3250p as listed on page 76 .
8 8023as?avr?12/06 atmega325p/3250p 2.3.12 reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not runni ng. the minimum pulse length is given in ?system and reset characterizations? on page 309 . shorter pulses are not guaranteed to generate a reset. 2.3.13 xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit. 2.3.14 xtal2 output from the invert ing oscillator amplifier. 2.3.15 avcc avcc is the supply voltage pin for port f and the a/d converter. it should be externally con- nected to v cc , even if the adc is not used. if the adc is used, it should be connected to v cc through a low-pass filter. 2.3.16 aref this is the analog reference pin for the a/d converter.
9 8023as?avr?12/06 atmega325p/3250p 3. resources a comprehensive set of development tools, app lication notes and datasheets are available for download on http:// www.atmel.com/avr.
10 8023as?avr?12/06 atmega325p/3250p 4. about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. for i/o registers located in extended i/o map, ?i n ?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructio ns that allow access to extended i/o. typically ?lds? and ?sts? combined with ? sbrs?, ?sbrc?, ?sbr?, and ?cbr?.
11 8023as?avr?12/06 atmega325p/3250p 5. register summary n ote: registers with bold type only available in atmega3250p. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved - - - - - - - - (0xfe) reserved - - - - - - - - (0xfd) reserved - - - - - - - - (0xfc) reserved - - - - - - - - (0xfb) reserved - - - - - - - - (0xfa) reserved - - - - - - - - (0xf9) reserved - - - - - - - - (0xf8) reserved - - - - - - - - (0xf7) reserved - - - - - - - - (0xf6) reserved - - - - - - - - (0xf5) reserved - - - - - - - - (0xf4) reserved - - - - - - - - (0xf3) reserved - - - - - - - - (0xf2) reserved - - - - - - - - (0xf1) reserved - - - - - - - - (0xf0) reserved - - - - - - - - (0xef) reserved - - - - - - - - (0xee) reserved - - - - - - - - (0xed) reserved - - - - - - - - (0xec) reserved - - - - - - - - (0xeb) reserved - - - - - - - - (0xea) reserved - - - - - - - - (0xe9) reserved - - - - - - - - (0xe8) reserved - - - - - - - - (0xe7) reserved - - - - - - - - (0xe6) reserved - - - - - - - - (0xe5) reserved - - - - - - - - (0xe4) reserved - - - - - - - - (0xe3) reserved - - - - - - - - (0xe2) reserved - - - - - - - - (0xe1) reserved - - - - - - - - (0xe0) reserved - - - - - - - - (0xdf) reserved - - - - - - - - (0xde) reserved - - - - - - - - (0xdd) portj - portj6 portj5 portj4 portj3 portj2 portj1 portj0 89 (0xdc) ddrj - ddj6 ddj5 ddj4 ddj3 ddj2 ddj1 ddj0 89 (0xdb) pi n j -pi n j6 pi n j5 pi n j4 pi n j3 pi n j2 pi n j1 pi n j0 89 (0xda) porth porth7 porth6 porth5 porth4 porth3 porth2 porth1 porth0 88 (0xd9) ddrh ddh7 ddh6 ddh5 ddh4 ddh3 ddh2 ddh1 ddh0 89 (0xd8) pi n hpi n h7 pi n h6 pi n h5 pi n h4 pi n h3 pi n h2 pi n h1 pi n h0 89 (0xd7) reserved - - - - - - - - (0xd6) reserved - - - - - - - - (0xd5) reserved - - - - - - - - (0xd4) reserved - - - - - - - - (0xd3) reserved - - - - - - - - (0xd2) reserved - - - - - - - - (0xd1) reserved - - - - - - - - (0xd0) reserved - - - - - - - - (0xcf) reserved - - - - - - - - (0xce) reserved - - - - - - - - (0xcd) reserved - - - - - - - - (0xcc) reserved - - - - - - - - (0xcb) reserved - - - - - - - - (0xca) reserved - - - - - - - - (0xc9) reserved - - - - - - - - (0xc8) reserved - - - - - - - - (0xc7) reserved - - - - - - - - (0xc6) udr0 usart0 data register 183 (0xc5) ubrr0h usart0 baud rate register high 187
12 8023as?avr?12/06 atmega325p/3250p (0xc4) ubrr0l usart0 baud rate register low 187 (0xc3) reserved - - - - - - - - (0xc2) ucsr0c - umsel0 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 185 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxe n 0txe n 0 ucsz02 rxb80 txb80 184 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 183 (0xbf) reserved - - - - - - - - (0xbe) reserved - - - - - - - - (0xbd) reserved - - - - - - - - (0xbc) reserved - - - - - - - - (0xbb) reserved - - - - - - - - (0xba) usidr usi data register 200 (0xb9) usisr usisif usioif usipf usidc usic n t3 usic n t2 usic n t1 usic n t0 200 (0xb8) usicr usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc 201 (0xb7) reserved - - - - - - - - (0xb6) assr - - - exclk as2 tc n 2ub ocr2ub tcr2ub 152 (0xb5) reserved - - - - - - - - (0xb4) reserved - - - - - - - - (0xb3) ocr2a timer/counter 2 output compare register a 152 (0xb2) tc n t2 timer/counter2 152 (0xb1) reserved - - - - - - - - (0xb0) tccr2a foc2a wgm20 com2a1 com2a0 wgm21 cs22 cs21 cs20 150 (0xaf) reserved - - - - - - - - (0xae) reserved - - - - - - - - (0xad) reserved - - - - - - - - (0xac) reserved - - - - - - - - (0xab) reserved - - - - - - - - (0xaa) reserved - - - - - - - - (0xa9) reserved - - - - - - - - (0xa8) reserved - - - - - - - - (0xa7) reserved - - - - - - - - (0xa6) reserved - - - - - - - - (0xa5) reserved - - - - - - - - (0xa4) reserved - - - - - - - - (0xa3) reserved - - - - - - - - (0xa2) reserved - - - - - - - - (0xa1) reserved - - - - - - - - (0xa0) reserved - - - - - - - - (0x9f) reserved - - - - - - - - (0x9e) reserved - - - - - - - - (0x9d) reserved - - - - - - - - (0x9c) reserved - - - - - - - - (0x9b) reserved - - - - - - - - (0x9a) reserved - - - - - - - - (0x99) reserved - - - - - - - - (0x98) reserved - - - - - - - - (0x97) reserved - - - - - - - - (0x96) reserved - - - - - - - - (0x95) reserved - - - - - - - - (0x94) reserved - - - - - - - - (0x93) reserved - - - - - - - - (0x92) reserved - - - - - - - - (0x91) reserved - - - - - - - - (0x90) reserved - - - - - - - - (0x8f) reserved - - - - - - - - (0x8e) reserved - - - - - - - - (0x8d) reserved - - - - - - - - (0x8c) reserved - - - - - - - - (0x8b) ocr1bh timer/counter1 output compare register b high 133 (0x8a) ocr1bl timer/counter1 output compare register b low 133 (0x89) ocr1ah timer/counter1 output compare register a high 133 (0x88) ocr1al timer/counter1 output compare register a low 133 (0x87) icr1h timer/counter1 input capture register high 134 (0x86) icr1l timer/counter1 input capture register low 134 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
13 8023as?avr?12/06 atmega325p/3250p (0x85) tc n t1h timer/counter1 high 133 (0x84) tc n t1l timer/counter1 low 133 (0x83) reserved - - - - - - - - (0x82) tccr1c foc1a foc1b - - - - - -132 (0x81) tccr1b ic n c1 ices1 - wgm13wgm12cs12cs11cs10 131 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 - -wgm11wgm10129 (0x7f) didr1 - - - - - -ai n 1d ai n 0d 206 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d 223 (0x7d) reserved - - - - - - - - (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 219 (0x7b) adcsrb -acme - - - adts2 adts1 adts0 205/223 (0x7a) adcsra ade n adsc adate adif adie adps2 adps1 adps0 221 (0x79) adch adc data register high 222 (0x78) adcl adc data register low 222 (0x77) reserved - - - - - - - - (0x76) reserved - - - - - - - - (0x75) reserved - - - - - - - - (0x74) reserved - - - - - - - - (0x73) pcmsk3 -pci n t30 pci n t29 pci n t28 pci n t27 pci n t26 pci n t25 pci n t24 63 (0x72) reserved - - - - - - - - (0x71) reserved - - - - - - - - (0x70) timsk2 - - - - - - ocie2a toie2 153 (0x6f) timsk1 - -icie1 - - ocie1b ocie1a toie1 134 (0x6e) timsk0 - - - - - - ocie0a toie0 105 (0x6d) pcmsk2 pci n t23 pci n t22 pci n t21 pci n t20 pci n t19 pci n t18 pci n t17 pci n t16 63 (0x6c) pcmsk1 pci n t15 pci n t14 pci n t13 pci n t12 pci n t11 pci n t10 pci n t9 pci n t8 63 (0x6b) pcmsk0 pci n t7 pci n t6 pci n t5 pci n t4 pci n t3 pci n t2 pci n t1 pci n t0 63 (0x6a) reserved - - - - - - - - (0x69) eicra - - - - - -isc01isc0060 (0x68) reserved - - - - - - - - (0x67) reserved - - - - - - - - (0x66) osccal oscillator calibration register [cal7..0] 36 (0x65) reserved - - - - - - - - (0x64) prr - - - - prtim1 prspi psusart0 pradc 45 (0x63) reserved - - - - - - - - (0x62) reserved - - - - - - - - (0x61) clkpr clkpce - - - clkps3 clkps2 clkps1 clkps0 37 (0x60) wdtcr - - - wdce wde wdp2 wdp1 wdp0 52 0x3f (0x5f) sreg i t h s v n zc13 0x3e (0x5e) sph stack pointer high 15 0x3d (0x5d) spl stack pointer low 15 0x3c (0x5c) reserved - - - - - - - - 0x3b (0x5b) reserved - - - - - - - - 0x3a (0x5a) reserved - - - - - - - - 0x39 (0x59) reserved - - - - - - - - 0x38 (0x58) reserved - - - - - - - - 0x37 (0x57) spmcsr spmie rwwsb - rwwsre blbset pgwrt pgers spme n 270 0x36 (0x56) reserved 0x35 (0x55) mcucr jtd bods bodse pud - - ivsel ivce 57/86/256 0x34 (0x54) mcusr - - - jtrf wdrf borf extrf porf 51 0x33 (0x53) smcr - - - - sm2 sm1 sm0 se 44 0x32 (0x52) reserved - - - - - - - - 0x31 (0x51) ocdr idrd/ocdr7 ocdr6 ocdr5 o cdr4 ocdr3 ocdr2 ocdr1 ocdr0 229 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 205 0x2f (0x4f) reserved - - - - - - - - 0x2e (0x4e) spdr spi data register 163 0x2d (0x4d) spsr spif wcol - - - - - spi2x 163 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 161 0x2b (0x4b) gpior2 general purpose i/o register 27 0x2a (0x4a) gpior1 general purpose i/o register 27 0x29 (0x49) reserved - - - - - - - - 0x28 (0x48) reserved - - - - - - - - 0x27 (0x47) ocr0a timer/counter0 output compare a 105 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
14 8023as?avr?12/06 atmega325p/3250p n otes: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. n ote that, unlike most other avrs, the cbi and sbi instructions will only operate on the specif ied bit, and can therefore be used on regi sters containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 4. when using the i/o specific commands i n and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x 20 must be added to these addre sses. the atmega325p/3250p is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the i n and out instructions. for the extended i/o space fr om 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x26 (0x46) tc n t0 timer/counter0 105 0x25 (0x45) reserved - - - - - - - - 0x24 (0x44) tccr0a foc0a wgm00 com0a1 com0a0 wgm01 cs02 cs01 cs00 103 0x23 (0x43) gtccr tsm - - - - - psr2 psr10 106/154 0x22 (0x42) eearh - - - - - eeprom address register high 23 0x21 (0x41) eearl eeprom address register low 23 0x20 (0x40) eedr eeprom data register 23 0x1f (0x3f) eecr - - - - eerie eemwe eewe eere 24 0x1e (0x3e) gpior0 general purpose i/o register 28 0x1d (0x3d) eimsk pcie3 pcie2 pcie1 pcie0 - - -i n t0 61 0x1c (0x3c) eifr pcif3 pcif2 pcif1 pcif0 - - -i n tf0 62 0x1b (0x3b) reserved - - - - - - - - 0x1a (0x3a) reserved - - - - - - - - 0x19 (0x39) reserved - - - - - - - - 0x18 (0x38) reserved - - - - - - - - 0x17 (0x37) tifr2 - - - - - -ocf2atov2154 0x16 (0x36) tifr1 - -icf1 - -ocf1bocf1atov1134 0x15 (0x35) tifr0 - - - - - -ocf0atov0106 0x14 (0x34) portg - - - portg4 portg3 portg2 portg1 portg0 88 0x13 (0x33) ddrg - - - ddg4 ddg3 ddg2 ddg1 ddg0 88 0x12 (0x32) pi n g - -pi n g5 pi n g4 pi n g3 pi n g2 pi n g1 pi n g0 88 0x11 (0x31) portf portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 88 0x10 (0x30) ddrf ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 88 0x0f (0x2f) pi n fpi n f7 pi n f6 pi n f5 pi n f4 pi n f3 pi n f2 pi n f1 pi n f0 88 0x0e (0x2e) porte porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 87 0x0d (0x2d) ddre dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 87 0x0c (0x2c) pi n epi n e7 pi n e6 pi n e5 pi n e4 pi n e3 pi n e2 pi n e1 pi n e0 88 0x0b (0x2b) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 87 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 87 0x09 (0x29) pi n dpi n d7 pi n d6 pi n d5 pi n d4 pi n d3 pi n d2 pi n d1 pi n d0 87 0x08 (0x28) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 87 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 87 0x06 (0x26) pi n cpi n c7 pi n c6 pi n c5 pi n c4 pi n c3 pi n c2 pi n c1 pi n c0 87 0x05 (0x25) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 86 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 86 0x03 (0x23) pi n bpi n b7 pi n b6 pi n b5 pi n b4 pi n b3 pi n b2 pi n b1 pi n b0 86 0x02 (0x22) p o rta p o rta 7 p o rta 6 p o rta 5 p o rta 4 p o rta 3 p o rta 2 p o rta 1 p o rta 0 8 6 0x01 (0x21) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 86 0x00 (0x20) pi n api n a7 pi n a6 pi n a5 pi n a4 pi n a3 pi n a2 pi n a1 pi n a0 86 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
15 8023as?avr?12/06 atmega325p/3250p 6. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c, n ,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c, n ,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c, n ,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c, n ,v,h 1 subi rd, k subtract constant from register rd rd - k z,c, n ,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c, n ,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c, n ,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c, n ,v,s 2 a n d rd, rr logical a n d registers rd rd ? rr z, n ,v 1 a n di rd, k logical a n d register and constant rd rd ? kz, n ,v 1 or rd, rr logical or registers rd rd v rr z, n ,v 1 ori rd, k logical or register and constant rd rd v k z, n ,v 1 eor rd, rr exclusive or registers rd rd rr z, n ,v 1 com rd one?s complement rd 0xff ? rd z,c, n ,v 1 n eg rd two?s complement rd 0x00 ? rd z,c, n ,v,h 1 sbr rd,k set bit(s) in register rd rd v k z, n ,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z, n ,v 1 i n c rd increment rd rd + 1 z, n ,v 1 dec rd decrement rd rd ? 1 z, n ,v 1 tst rd test for zero or minus rd rd ? rd z, n ,v 1 clr rd clear register rd rd rd z, n ,v 1 ser rd set register rd 0xff n one 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 n one 2 ijmp indirect jump to (z) pc z n one 2 jmp k direct jump pc k n one 3 rcall k relative subroutine call pc pc + k + 1 n one 3 icall indirect call to (z) pc z n one 3 call k direct subroutine call pc k n one 4 ret subroutine return pc stack n one 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 n one 1/2/3 cp rd,rr compare rd ? rr z, n ,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n ,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n ,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 n one 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 n one 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 n one 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 n one 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 n one 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 n one 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 n one 1/2 br n e k branch if n ot equal if (z = 0) then pc pc + k + 1 n one 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 n one 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 n one 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 n one 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 n one 1/2 brmi k branch if minus if ( n = 1) then pc pc + k + 1 n one 1/2 brpl k branch if plus if ( n = 0) then pc pc + k + 1 n one 1/2 brge k branch if greater or equal, signed if ( n v= 0) then pc pc + k + 1 n one 1/2 brlt k branch if less than zero, signed if ( n v= 1) then pc pc + k + 1 n one 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 n one 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 n one 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 n one 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 n one 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 n one 1/2
16 8023as?avr?12/06 atmega325p/3250p brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 n one 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 n one 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 n one 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1 n one 2 cbi p,b clear bit in i/o register i/o(p,b) 0 n one 2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c, n ,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c, n ,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c, n ,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c, n ,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c, n ,v 1 swap rd swap n ibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) n one 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t n one 1 sec set carry c 1c1 clc clear carry c 0 c 1 se n set n egative flag n 1 n 1 cl n clear n egative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr n one 1 movw rd, rr copy register word rd+1:rd rr+1:rr n one 1 ldi rd, k load immediate rd k n one 1 ld rd, x load indirect rd (x) n one 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 n one 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) n one 2 ld rd, y load indirect rd (y) n one 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 n one 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) n one 2 ldd rd,y+q load indirect with displacement rd (y + q) n one 2 ld rd, z load indirect rd (z) n one 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 n one 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) n one 2 ldd rd, z+q load indirect with displacement rd (z + q) n one 2 lds rd, k load direct from sram rd (k) n one 2 st x, rr store indirect (x) rr n one 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 n one 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr n one 2 st y, rr store indirect (y) rr n one 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 n one 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr n one 2 std y+q,rr store indirect with displacement (y + q) rr n one 2 st z, rr store indirect (z) rr n one 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 n one 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr n one 2 std z+q,rr store indirect with displacement (z + q) rr n one 2 sts k, rr store direct to sram (k) rr n one 2 lpm load program memory r0 (z) n one 3 lpm rd, z load program memory rd (z) n one 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 n one 3 spm store program memory (z) r1:r0 n one - i n rd, p in port rd p n one 1 out p, rr out port p rr n one 1 mnemonics operands description operation flags #clocks
17 8023as?avr?12/06 atmega325p/3250p push rr push register on stack stack rr n one 2 pop rd pop register from stack rd stack n one 2 mcu control instructions n op n o operation n one 1 sleep sleep (see specific descr. for sleep function) n one 1 wdr watchdog reset (see specific descr. for wdr/timer) n one 1 break break for on-chip debug only n one n /a mnemonics operands description operation flags #clocks
18 8023as?avr?12/06 atmega325p/3250p 7. ordering information n otes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. 3. for speed vs. v cc see figure 25-1 on page 307 and figure 25-2 on page 307 . 7.1 atmega325p speed (mhz) (3) power supply ordering code (2) package type (1) operational range 10 1.8 - 5.5v atmega325pv-10au atmega325pv-10mu 64a 64m1 industrial (-4 0 c to 85 c) 20 2.7 - 5.5v ATMEGA325P-20AU atmega325p-20mu 64a 64m1 industrial (-4 0 c to 85 c) package type 64a 64-lead, 14 x 14 x 1.0 mm, thin profile plastic quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0 mm, quad flat n o-lead/micro lead frame package (qf n /mlf)
19 8023as?avr?12/06 atmega325p/3250p n otes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. 3. for speed vs. v cc see figure 25-1 on page 307 and figure 25-2 on page 307 . 7.2 atmega3250p speed (mhz) (3) power supply ordering code (2) package type (1) operational range 10 1.8 - 5.5v atmega3250pv-10au 100a industrial (-4 0 c to 85 c) 20 2.7 - 5.5v atmega3250p-20au 100a industrial (-4 0 c to 85 c) package type 100a 100-lead, 14 x 14 x 1.0 mm, 0.5 mm lead pitch, thin profile plastic quad flat package (tqfp)
20 8023as?avr?12/06 atmega325p/3250p 8. packaging information 8.1 64a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64a, 64-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 64a 10/5/2001 pi n 1 ide n tifier 0?~7? pi n 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note n otes: 1. this package conforms to jedec reference ms-026, variation aeb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 n ote 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 n ote 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
21 8023as?avr?12/06 atmega325p/3250p 8.2 64m1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64m1 , 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, g 64m1 5/25/06 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 b 0.18 0.25 0.30 d d2 5.20 5.40 5.60 8.90 9.00 9.10 8.90 9.00 9.10 e e2 5.20 5.40 5.60 e 0.50 bsc l 0.35 0.40 0.45 note: 1. jedec standard mo-220, (saw singulation) fig. 1, vmmd. 2. dimension and tolerance conform to asmey14.5m-1994. top view s ide view bottom view d e marked pin# 1 id seating plane a1 c a c 0.08 1 2 3 k 1.25 1.40 1.55 e2 d2 b e pin #1 corner l pin #1 triangle pin #1 chamfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k 5.40 mm exposed pad, micro lead frame package (mlf)
22 8023as?avr?12/06 atmega325p/3250p 8.3 100a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 100a, 100-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.5 mm lead pitch, thin profile plastic quad flat package (tqfp) c 100a 10/5/2001 pi n 1 ide n tifier 0?~7? pi n 1 l c a1 a2 a d1 d e e1 e b a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 n ote 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 n ote 2 b 0.17 ? 0.27 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.50 typ n otes: 1. this package conforms to jedec reference ms-026, variation aed. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.08 mm maximum. common dimensions (unit of measure = mm) symbol min nom max note
23 8023as?avr?12/06 atmega325p/3250p 9. errata 9.1 atmega325p rev. a ? interrupts may be lost when writing the timer registers in th e asynchronous timer. 1. interrupts may be lost when writing the timer registers in the asynchronous timer. if one of the timer registers which is synchroni zed to the asynchronous timer2 clock is writ- ten in the cycle before a overflow interr upt occurs, the interrupt may be lost. problem fix/workoround always check that the timer2 timer/counter register, tc n t2, does not have the value 0xff before writing the ti mer2 control register, tccr2, or output compare register, ocr2. 9.2 atmega3250p rev. a ? interrupts may be lost when writing the timer registers in th e asynchronous timer. 1. interrupts may be lost when writing the timer registers in the asynchronous timer. if one of the timer registers which is synchroni zed to the asynchronous timer2 clock is writ- ten in the cycle before a overflow interr upt occurs, the interrupt may be lost. problem fix/workoround always check that the timer2 timer/counter register, tc n t2, does not have the value 0xff before writing the ti mer2 control register, tccr2, or output compare register, ocr2.
24 8023as?avr?12/06 atmega325p/3250p 10. datasheet revision history please note that the referring page numbers in this section are referring to this document.the referring revision in this section are referring to the document revision. 10.1 rev.8023a ? 12/06 1. initial version.
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